Future Avalanche Board Mi-V Sample FPGA Designs

This folder contains Tcl scripts that build Libero SoC v2024.2 design projects for the Future Avalanche Board. These scripts are executed in Libero SoC to generate the sample designs. All Configuration (CFG) design cores boot from memory at 0x8000_0000.

MI-V Extended Subsystem Design Guide Configurations:

For Design Guide Configuration - DGC2: I2C Write & Boot refer to this DGC2 README

PF_Avalanche_MIV_RV32_BaseDesign

Config	Description
CFG1	This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IMC</li><li>Multiplier: MACC (Pipelined)</li><li>Interfaces: AHBL Initiator (mirrored), APB3 Initiator</li><li>Internal IRQs: 1</li><li>TCM: enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li><li>An example program is stored in the LSRAM to boot out the box</ul>
CFG2	This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IM</li><li>Multiplier: Fabric</li><li>Interfaces: AXI4 Master (mirrored), APB3 Initiator</li><li>Internal IRQs: 1</li><li>TCM: Disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li><li>An example program is stored in the LSRAM to boot out the box</ul>
CFG3	This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: I</li><li>Multiplier: none</li><li>Interfaces: APB3 Initiator</li><li>Internal IRQs: 1</li><li>TCM: enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li></ul>

Instructions

Running Libero SoC in GUI mode

Open Libero SoC
Execute the script, Project -> Execute Script
Select the directory that the script is located in using the "..."
Select the script and select "Open"
In the arguments text box, enter the type of configuration you want e.g. "CFG1"
Select the "Run" button to execute the script
Once complete, a script report will be generated.

Libero executes the script and opens the Mi-V sample project targeted for a production silicon (PS) die. The script adds Timing constraints to the project for Synthesis, Place and Route, and Timing Verification. Additionally, I/O Constraints are added to the project for Place and Route. The project can now be taken through the remainder of the Libero SoC design flow.

Running Libero SoC in GUI mode, with Script Arguments

Open Libero SoC
Execute the selected script, Project -> Execute Script
Select the directory that the script is located in, using the "..."
Select the script and select "Open"
In the arguments text box, enter "CFG1 SYNTHESIZE PS"
Select the "Run" button to execute the script
Once complete, a script report will be generated.

In this example, the arguments “CFG1 SYNTHESIZE PS” are entered to take the production silicon (PS) die project through to Synthesis.

Script Arguments

In the examples above the arguments “CFG1” and “CFG1 SYNTHESIZE PS” were entered. The complete set of script arguments are documented here.

First argument:

Second argument:

Third argument:

| Argument | Description | | ————————- |:—————| | PS | Build a base design targeted for ‘PS’ die | | ES | Build a base design targeted for ‘ES’ die |

Design Features

The Libero designs include the following features:

A soft RISC-V processor operating at 50 MHz
A RISC-V debug block allowing on-target debug using SoftConsole
An Extended Subsystem with integrated peripherals
Target SRAM/TCM memory (32kB)
User peripherals: MIV_ESS, 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)

The peripherals in this design are located at the following addresses.

MIV_RV32 based configurations